As integrated devices continue to scale to smaller dimensions, the ability to pattern features becomes increasingly difficult. These difficulties include, in one aspect, the ability to etch features to preserve or transfer a pattern into a substrate. In many device applications, a patterned feature may have a smallest dimension less than 50 nm and in some cases the smallest dimension may be less than 10 nm. Moreover, the thickness of layers to be etched for building and patterning device structures may be less than 10 nm in some examples.
One technique developed to controllably etch thin layers is atomic layer etching (ALE) where etching takes place on a layer-by-layer basis. In a first operation, in an ALE apparatus a first reactant, such as a reactive gas, may be introduced to a substrate where the first reactant forms a self-limiting monolayer on a surface of the substrate. The self-limiting monolayer may include the first reactant and the upper layer of material from the substrate. Subsequently, the first reactant may be purged from the ALE system and in a further operation an etchant may be provided to remove the self-limiting monolayer. In this manner, one monolayer of a substrate may be etched at a time, providing accurate control of the amount of material to be removed.
One problem with the ALE process is the relatively slow rate of processing a substrate, since several operations are involved to etch one monolayer, including the time for purging a reactant material. Additionally, the removal of a self-limiting monolayer in known ALE processes may be suitable for etching planar structures, while providing less capability for etching non-planar structures, such as three dimensional (3D) structures where geometric selectivity is desired.
With respect to these and other considerations the present improvements may be useful.